Semiconductor memories, such as dynamic random access memories (DRAMs) comprise an array of memory cells that are interconnected by rows (wordlines) and columns (bit lines). In general, the memory cells comprise storage nodes that are formed within deep trenches etched into a semiconductor substrate. The storage nodes are accessed using a transistor, which allows a charge to be stored in the storage node or to be retrieved from the storage node, depending on the desired action (i.e., read or write).
In general, a transistor of a DRAM memory cell comprises two diffusion regions isolated from one another by a channel which is controlled by a gate. Depending on the direction of the flow of current, one diffusion region is called the drain region and the other diffusion region is called the source region. One of the diffusion regions is connected to a bit line, the other diffusion region is connected to the cell capacitor (storage node), and the gate is connected to a word line. By applying suitable voltages to the gate, the transistor is controlled such that a flow of current between the diffusion regions through the channel is turned on and off.
Typically, a DRAM memory cell comprises a MOSFET (metal oxide semiconductor field effect transistor) connected to a capacitor. There are different types of MOSFETs. A planar MOSFET is a transistor where a surface of the channel region of the transistor is generally parallel to the primary surface of the substrate. A vertical MOSFET is a transistor where a surface of the channel region of the transistor is generally perpendicular to the primary surface of the substrate.
Due to technological advancements that enable fabrication of increasingly smaller memory device components, the integration density of memory cells is continuously increasing. With increasing density, planar transistors (such as MOSFETS) in trench storage memory devices are limited in terms of scalability due to the critical dimension of the gate length having to be no less than about 110 nm, to avoid performance degradation or sensitivity to process tolerances.
Accordingly, to utilize the available area effectively, state of the art trench capacitor DRAMs have been implemented using memory cells with vertical transistors, wherein a transistor is stacked above a trench capacitor. Vertical transistors provide significant scalability, especially below minimum feature sizes of about 100 nm. This is due in part to the vertical channel length for the vertical transistor being decoupled from the minimum design ground rule.
Various techniques have been developed for forming vertical transistors for semiconductor memory cells. As with all new technologies, however, opportunities exist for improving the structure and process of integration of memory cells comprising vertical transistors. One area for improvement in the design of a vertical transistor concerns effectively isolating the vertical gate conductor from shorting to, e.g., a bitline contact (or other upper layers). More specifically, it is very important to provide proper separation between the vertical gate conductor which connects to a wordline, for example, and a bitline contact which contacts a diffusion region (drain/source) adjacent the vertical gate conductor.
FIGS. 1A–1H illustrate a conventional method for forming a memory cell comprising a vertical transistor device and deep trench capacitor. FIG. 1A schematically illustrates a cross-sectional view of memory cell at an intermediate stage of fabrication of the memory cell. In particular, FIG. 1A illustrates a silicon substrate (1) which comprises a P-substrate (2), which has undergone various processes such as deep trench processing, buried strap formation, active area processing, ion dopant implantation, etc., using one or more methods known to those of ordinary skill in the art, to form a buried N well (3), P well (4) (or device well), a deep trench (5), a buried plate (10), collars (12), a node dielectric (13), a storage node (14), a buried strap (15), a TTO (trench top oxide) (16), buried strap diffusion regions (17), bitline diffusion regions (18), a pad oxide layer (11), a pad nitride layer (19) and a gate oxide layer (20).
The deep trench (5) is formed in the substrate (1) using conventional processes well-known to those of ordinary skill in the art. For example, as is known in the art, a mask oxide layer (not shown) can be formed over the pad stack (e.g., pad nitride (19) and pad oxide (11)) and patterned for use as an etch mask for etching an array of deep trenches in the substrate (1). The trench (5) is etched to about 5 um to about 10 um below the surface of the substrate (1). The substrate (1) may comprise a monocrystalline substrate (silicon, SiGe, GaAs, etc.) which is doped to form P-well (4), which is the exemplary embodiment is a device well.
FIG. 1A illustrates a trench capacitor that is formed in a lower portion of the trench (5) below the trench top oxide (16). In particular, the trench capacitor comprises storage node (14), which represents a first capacitor plate, buried plate (10), which represent a second capacitor plate, and the node dielectric (13). Various methods for forming the trench capacitor are well-known in the art. Briefly, after the trench (5) is formed, the buried plate (10) is formed by diffusing N+ dopants out from a dopant source into a portion of the substrate (1) surrounding the lower portion of the trench (5). The node dielectric layer (13) is conformally deposited and etched to line bottom of the trench (5). The node dielectric (13) may be a nitride oxide layer or any other material suitable for use as a capacitor dielectric.
The oxide collars (12) are formed on the sidewalls of the trench (5) using LOCOS (localized silicon oxidation), TEOS deposition, or other collar forming methods known in the art. The trench (5) is filled with a conductive material such as polycrystalline silicon (poly) or amorphous silicon, N+ doped polysilicon, to form the storage node (14). The storage node (14) and oxide collars (12) are recessed/planarized to a desired depth and the buried strap (15) is formed. The buried strap (15) provides a connection between the storage node (14) and the P well (4) regions of the substrate (10). The oxide collars (12) act to isolate contact of the N+ polysilicon (14) to the substrate (1).
The TTO (trench top oxide) (16) is formed on top of the buried strap (15) to provide isolation between the storage node (14) and a gate conductor (shown in FIG. 1B) of a vertical transistor, which is formed in the upper portion of the trench (5) above the TTO (16). Methods for forming the TTO layer (16) are well-known in the art. For instance, an oxide (silicon dioxide) is deposited on horizontal surfaces using HDP (high density plasma) process, whereby oxide deposition fills in from the bottom to the top, to form an oxide layer over the polysilicon (14) in the trench (5) and on the horizontal surfaces of the substrate. Other portions of the deposited oxide are removed by planarizing the surface of the semiconductor device and/or by recessing the oxide using a wet etch to leave about a 30–50 nm thick oxide layer at the bottom of the recess, which forms the trench top oxide (16).
As is known in the art, the buried strap (15) is used to form the strap diffusion regions (17), whereby dopants from the buried strap (15) region of the polysilicon storage node (14) are outdiffused into the P-well (4) portion of the substrate (1) during a thermal process. It is preferable for the strap diffusion regions (17) to overlap the TTO (16) to be at least coincident with the edge of a vertical gate conductor (e.g., gate conductor (21) shown in FIG. 1B) of the vertical transistor.
The strap diffusion regions (17) essentially act as source/drain terminals for a vertical transistor. More specifically, the strap diffusion regions (17) are access nodes to the storage node (14), providing electrical connection between a vertical transistor and the storage node (14). A diffusion region (17) is electrically connected to a bitline diffusion region (18) via a vertical transistor channel (not shown) which is formed in the P well (4) of the substrate (1) extending along the gate oxide (20) on the sidewalls of the upper portion of the trench (5) above the TTO (16), when the vertical transistor is activated. The channel must be electrically isolated from the vertical gate conductor. Therefore, an insulating layer is provided, typically an oxide layer formed by oxidizing single crystalline silicon within the deep trench and the channel.
A vertical transistor is formed in the region of the substrate above the TTO (16), which separates the vertical transistor from the buried strap (15). In particular, FIG. 1A illustrates an intermediate stage of fabrication of a memory cell where various components of a vertical transistor are formed. For instance, the bit line diffusion regions (18) are formed in the substrate (5) by implanting dopants (preferably N+ dopants, although other dopants may be used depending on the design) using methods known to those of ordinary skill in the art.
The gate oxide layer (20) (gate dielectric) is formed on the vertical sidewalls of the upper portion (vertical gate region) of the trench (5) (and optionally on top of the TTO (16)) using, e.g., a furnace oxidation process or any other suitable process depending on the type of oxide used. For example, the gate dielectric (20) can be formed by heating the substrate in the presence of oxygen to form an oxide layer on the exposed surfaces of the substrate, an in particular, the vertical sidewalls of the trench (5). During this thermal process, the strap diffusion regions (17) may be formed. Moreover, during this process, the surface of the pad nitride (19) is oxidized, which can lead to device failures as described later.
Referring now to FIG. 1B, after the gate dielectric (20) is formed on the vertical trench sidewalls, a gate polysilicon (21) (or gate poly fill) is formed in the upper portion of the trench (5) (i.e., the vertical gate region) above the TTO (16). The gate polysilicon (21) can be formed by depositing a layer of polysilicon over the substrate to fill the entire upper portion of the trench (5). For instance, N+ doped polysilicon can be deposited using an in situ CVD (chemical vapor deposition) process such as LPCVD (low pressure CVD). Alternatively, intrinsic polysilicon can also be deposited by CVD techniques, and subsequently doped to form N+ doped polysilicon within the vertical gate region. The polysilicon is then etched back using a poly recess method known to those of ordinary skill in the art. For instance, a CMP (chemical mechanical polish) process is performed to planarize the substrate to the top surface of the pad nitride (19). The remaining polysilicon is then recessed using a wet etch that is selective to the pad nitride (19) (or RIE (reactive ion etch), such that the polysilicon is recessed to a desired level below the surface of the substrate (1).
The result of such process (as shown in FIG. 1B) is formation of the gate polysilicon (21), which is recessed below the substrate (1) surface to a level that overlaps the diffusion regions (18). An oxidation process can then performed to oxidize the surface of the polysilicon (21), which forms an oxidation layer (not shown) that can be used as an etch stop in a subsequent process of spacer formation. This process further oxidizes the surface of the pad nitride layer (19).
Referring to FIG. 1C, a conformal layer of nitride (22) is deposited over the substrate (1) such that the conformal nitride layer (22) occupies about ⅔ of the width of the trench. The conformal nitride layer (22) can be formed using LPCVD, for example, or other methods known to those of ordinary skill in the art.
Referring to FIG. 1D, nitride spacers (23) are formed on the vertical sidewalls of the trench above the gate poly fill (21) and on the vertical sidewalls of the pad nitride (19). For example, the nitride spacers (23) can be formed by etching the conformal nitride layer (22) down to the pad nitride (19) and the gate poly fill (21) layers using an anisotropic etch process, such as RIE (Reactive Ion Etching). As is known in the art, such nitride etch process results in nitride spacers (23) having a rounded upper edge (not a true vertical rise). Furthermore, the nitride spacer formation process results in formation of an aperture (24) down to the surface of the poly fill (21).
Referring to FIG. 1E, a poly contact plug (25) is formed in the aperture (24). The poly contact plug (25) can be formed by depositing a layer of polysilicon over the substrate to fill the aperture (24) followed by an etching or recess process to etch back the polysilicon layer to the top of the pad nitride (19), thereby forming the poly contact plug (25). The poly contact plug (25) may be etched back to be at or below the surface of the pad nitride (19). The gate contact plug (25) and gate poly fill (21) form the vertical gate conductor of a vertical transistor. In subsequent processing steps, the contact plug (25) is electrically connected to, e.g., a wordline.
Referring to FIG. 1F, a pad nitride strip process is performed to remove the pad nitride (19). For example, an isotropic wet etch process is performed for stripping pad nitride (19). In this process, the nitride spacer (23) is also removed forming a divot (23a) (or spacer region). As depicted in FIG. 1F, the conventional process results in formation of a filament (19a) that dangles over the divot (23a). The filament (19a) comprises oxidized nitride, which results from the oxidation of the vertical sidewalls of the pad nitride (19) during previous processing steps for forming the gate oxide (20) on the trench sidewalls and/or the oxidation layer over the poly fill layer (21).
Referring to FIG. 1G, after removal of the pad nitride (19) and nitride spacers (23), a nitride refill process is performed by isotropically depositing a layer of silicon nitride (26) to fill the divot around the plug (25). However, as depicted in FIG. 1G, the filament (19a) prevents the proper divot fill of the spacer nitride, resulting in voids (27) in the nitride that fills the divot (23a). More specifically, the combination of the filament (19a) and flared upper portion of the contact plug (25) reduces the opening to the divot (23a), which can prevent proper divot fill resulting in the formation of voids (27).
Referring to FIG. 1H, the nitride refill layer (26) is anisotropically etched using, e.g., RIE, to remove the nitride layer (26) down to the pad oxide (11) and form a nitride spacer (26a). In this process, the filament (19a) is substantially or completely removed. The result of the conventional process as depicted in FIG. 1H is nitride spacer (26a) having voids (27) formed therein. The process continues using methods well-known to those of ordinary skill in the art to connect the vertical gate conductor to a wordline and connecting one or both of the bitline diffusion regions (18) to a bitline.
There are various disadvantages associated with the conventional process described above with respect to isolation and alignment of the vertical gate conductor, which can cause defects in the memory cell that result in electrical shorts (e.g., connection between the vertical gate conductor (wordline) and bitline). For instance, the conventional process described above can cause oxidation of the vertical sidewalls of the pad nitride (19), which as depicted in FIG. 1H, can result in the formation of a filament (19a) overhanging the spacer region or divot (23a) which is be filled with nitride. The filament (19a) can prevent the proper divot fill of the spacer nitride when the layer of nitride (26) is deposited, resulting in voids (27) in the resulting nitride spacers (26a) (FIG. 1H). These voids (27) may be filled with polysilicon in subsequent deposition steps which can lead to shorts between the gate (wordline) and bitline.
Moreover, as shown in FIG. 1E, for example, the vertical gate conductor contact plug (25) which is formed between nitride spacers (23) does not have vertical sidewalls and the plug (25) is wider at its top surface due to the rounded upper surface of the nitride spacers (23). Since the width (or diameter) of the upper surface of the contact plug (25) is not well-defined, misalignments can occur between the gate contact plug (25) and wordline, which can result in shorts.
Accordingly, there is a need for an improved method of forming a vertical transistor, which overcomes the above problems of creating shorts due to voids in nitride spacers being filled with polysilicon and misalignment of the wordline and vertical gate contacts.